Complementary metal oxide semiconductor (CMOS) comprises P-channel metal oxide semiconductor (PMOS, Positive channel Metal Oxide Semiconductor) and N-Channel metal oxide semiconductor (NMOS, Negative channel Metal Oxide Semiconductor).
At present, semiconductor layers in a PMOS region and an NMOS region in a CMOS circuit are generally prepared separately by a low temperature polysilicon technology (LTPS), the preparation is relatively complex, and the specific process steps are as follows.
In step 1: On a base substrate 01, a pattern of a PMOS semiconductor layer 02 in a PMOS region A and a pattern of an NMOS semiconductor layer 03 in an NMOS region B are formed by a patterning process, as shown in FIG. 1a; 
wherein, the preparation of the PMOS semiconductor layer 02 and NMOS semiconductor layer 03 particularly includes: a layer of a-Si material is formed on the base substrate 01, a polysilicon material is generated after a laser crystallization is applied to the layer of a-Si material, and then the pattern of the PMOS semiconductor layer 02 and the pattern of the NMOS semiconductor layer 03 are formed with the polysilicon material through a patterning process;
In step 2: a gate insulating layer 04 is formed on the PMOS semiconductor layer 02 and the NMOS semiconductor layer 03, a gate material is deposited on the gate insulating layer 04, and then a pattern of a PMOS gate 05 in the PMOS region A and a pattern of an NMOS gate 06 in the NMOS region B are formed through a patterning process, as shown in FIG. 1b; 
In step 3: the PMOS semiconductor layer 02 is doped with P type ions, in particular, a pattern of a doping barrier layer 07 is formed on the NMOS gate 06 through a patterning process for covering the NMOS region B, as shown in FIG. 1c; P type ions are injected into the base substrate 01 with the doping barrier layer 07, and P-type doped polysilicon is formed in the regions of the PMOS semiconductor layer 02 uncovered by the PMOS gate 05, as shown in FIG. 1d; and after the injection of P type ions, the doping barrier layer 07 is stripped.
In step 4: the NMOS semiconductor layer 03 is doped with N type ions, the particular process for N type ion doping is same as that for the P type ion doping, and detailed description is omitted herein.
In step 5: a LDD (Lightly-Doped-Drain) doping process and a Ch (Channel) doping process are applied to the NMOS semiconductor layer sequentially, and both of the LDD doping process and the Ch doping process are similar to the P type ion doping process, the detailed description is omitted herein.
In step 6: a pattern of an interlayer dielectric layer 08 is formed on the PMOS gate and the NMOS gate through a patterning process, as shown in FIG. 1e. 
In step 7: a pattern of PMOS source/drain 09 in the PMOS region A and a pattern of NMOS source/drain 10 in the NMOS region B are formed on the interlayer dielectric layer 08 through a patterning process, as shown in FIG. 1f. 
Specifically, after completion of the above steps 1 to 7, the following steps are further required to be performed when the CMOS circuit is applied to an OLED panel.
In step 8: a pattern of a passivation layer 11 is formed on the PMOS source/drain 09 and the NMOS source/drain 10 through a patterning process, and a pattern of a planarization layer 12 is formed on the passivation layer 11 through a patterning process, as shown in FIG. 1g. 
In step 9: a pattern of a pixel layer used as an anode is formed on the planarization layer through a patterning process, the pixel layer is electrically connected to the source or the drain of the PMOS source/drain, as shown in FIG. 1h. 
In Step 10: a pattern of a pixel defining layer is formed on the pixel layer through a patterning process, as shown in FIG. 1i. 
In the preparation of the CMOS circuit with the LTPS process, at least 10 photolithography masks and at least four doping processes (P type ion doping, N type ion doping. LDD doping and Ch doping) are required, so the preparation is complex and has a high production cost; in addition, the entire layer of a-Si material is subject to laser crystallization to obtain the polysilicon material in step 1, such long-time laser crystallization process leads to an increased production cost and a reduced lifespan of a laser tube, which also contributes to the increased production cost.